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| [AK4186] AK4186 low power touch screen controller with i 2 c interface general description the AK4186 is a 4-wire/ 5-wire resistive touch screen controller that incorporates 12bit sar a/d converter. the AK4186 can detect th e pressed screen location with two a/d conversions and it can also measure touch pressure. the AK4186 has both an automatic continuous measurement and a measurement data calculation function. the functions that normally require external processing, such as calculating the average screen input value, are processed by the AK4186. in addition, a new sequential mode achieves short coordinate measurement time while greatly reducing the microprocessor overhead. the AK4186 operates off of supply voltage down to 1. 6v in order to connect a low voltage microprocessor. the AK4186 is the best fit for cellular phone, dsc, dvc, smart phone and other portable devices. features ! 4-wire or 5-wire touch screen interface 2 c serial interface ! i ! 12bit sar a/d converter with s/h circuit ! sampling rate: 22.2khz ! pen pressure measurement (4-wire) ! continuous read function ! integrated internal osc (sequence mode) ! integrated median averaging filter ! low voltage operation: vdd = 1.6v ~ 3.6v ! penirqn buffer output ! low power consumption: 60a at 1.8v ! auto power down ! package: 12pin csp (1.7mm x 1.3mm, pitch 0.4mm) 16pin qfn (3mm x 3mm, pitch 0.5mm) penirqn i 2 c se ria l i/f & control logic test vss ai n+ ai n- sda cad0 scl xp/br yp/tr xn/tl yn /bl in / wiper sar adc vdd 4/5wire touch screen drivers interface mu x vref+ vref- in ter na l osc figure 1. block diagram i 2 c-bus is a trademark of nxp b.v. ms1068-e-04 2011/03 - 1 -
[AK4186] ordering guide AK4186ecb ? 40 +85 c 12pin csp (1.66mm x 1.26mm, 0.4mm pitch) black type AK4186en ? 40 +85 c 16pin qfn (3mm x 3mm, 0.5mm pitch) akd4186 AK4186ecb evaluation board akd4186en AK4186en evaluation board pin layout AK4186ecb a bcd 3 1 2 ak 41 86 ecb top view 3 xp/br yp/tr xn/tl yn/bl 2 vdd cad0 test vss 1 in/wiper penirqn sda scl a b c d top view AK4186en nc vss test nc yn/bl xn/tl yp/tr xp/br scl sd a penir q cad0 nc vdd in/wiper nc AK4186en top view 13 14 15 1 6 12 11 10 1 8 7 6 5 9 2 3 4 ms1068-e-04 2011/03 - 2 - [AK4186] pin/function pin no. function ecb en pin name i/o d1 1 scl i i 2 c serial clock input c1 2 sda i/o i 2 c serial data input/ output b1 3 penirqn o pen interrupt output (cmos output) the penirqn pin is ?l? when touch-scre en press is detected. this pin is always ?l? irrespective of touch-screen press when pen interrupt is not enabled. b2 4 cad0 i i 2 c slave address bit 0 - 5 nc - no connection. no internal bonding. this pin must be connected to vss. in i auxiliary analog input (4-wire, panel bit = ?0?) a1 6 wiper i top touch panel input (5-wire, panel bit = ?1?) a2 7 vdd - power supply and external reference input: 1.6v ~ 3.6v - 8 nc - no connection. no internal bonding. this pin must be connected to vss. xp i/o touch panel x+ input (4-wire, panel bit = ?0?) a3 9 br i/o touch panel bottom right input (5-wire, panel bit = ?1?) yp i/o touch panel y+ input (4-wire, panel bit = ?0?) b3 10 tr i/o touch panel top right input (5-wire, panel bit = ?1?) xn i/o touch panel x- input (4-wire, panel bit = ?0?) c3 11 tl i/o touch panel top left inpu t (5-wire, panel bit = ?1?) yn i/o touch panel y- input (4-wire, panel bit = ?0?) d3 12 bl i/o touch panel bottom left i nput (5-wire, panel bit = ?1?) - 13 nc - no connection. no internal bonding. this pin must be connected to vss. d2 14 vss - ground c2 15 test i test pin this pin must be connected to vss. - 16 nc - no connection. no internal bonding. this pin must be connected to vss. note 1. all digital input pins (cad0, scl, sda) must not be left floating. ms1068-e-04 2011/03 - 3 - [AK4186] handling of unused pin the unused i/o pin must be processed appropriately as below. classification pin name setting analog in/wiper this pin must be open. absolute maximum ratings (vss = 0v ( note 2 )) parameter symbol min max units power supply vdd -0.3 4.6 v input current, any pins except for supply iin - ma 10 touch panel drive current ioutdrv - 50 ma input voltage ( note 3 ) vin vdd+0.3 or 4.6 v ? 0.3 ambient temperature (power applied) ta -40 85 c storage temperature tstg -65 150 c note 2. all voltages with respect to ground. note 3. xp/br, xn/tl, yp/tr, yn /tl, in/wiper, cad0, scl and sda pins. max is smaller value between (vdd+0.3)v and 4.6v. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommend operating conditions (vss = 0v ( note 2 )) parameter symbol min typ max units power supply vdd 1.6 1.8 3.6 v note 2. all voltages with respect to ground. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet. ms1068-e-04 2011/03 - 4 - [AK4186] analog characteristics (ta = -40 c to 85 c, vdd = 1.8v, i 2 c bus scl=400khz) parameter min typ max units a/d converter resolution - 12 - bits no missing codes 11 12 - bits integral nonlinearity (inl) error - - 2 lsb differential nonlinearity (dnl) error -2 1 +3 lsb offset error AK4186ecb - - 6 lsb AK4186en -4 - +8 lsb gain error AK4186ecb - - 4 lsb AK4186en -4.5 - +3.5 lsb throughput rate - - 22.2 khz touch panel drivers switch on-resistance xp, yp - 6 - ? xn, yn - 6 - ? penirq pull up resistor r - 50 - k ? irq auxiliary in input input voltage range 0 - vdd v power supply current vdd=1.8v - 60 - a normal mode (single mode, pd0 bit = ?0?) ( note 4 ) - - 220 vdd=3.6v a normal mode (sequence mode, 10khz equal rate) ( note 5 ) - 25 - a full power down (sda = scl = ?h?) 0 3 - a note 4. continuous adc data read (fs = 22.2khz). expect for power consumption of touch panel driver. note 5. count bit = ?1?, interval2-0 bits = 000. write command cycle = 1khz. expect for power consumption of touch panel driver. dc characteristtics (logic i/o) (ta=-40 c to 85 c, vdd =1.6v to 3.6v) parameter symbol min typ max units ?h? level input voltage vih 0.8xvdd - - v ?l? level input voltage vil - - 0.2xvdd v input leakage current iilk -10 - 10 a voh vdd-0.3 - - v ?h? level output voltage (penirqn pin @ iout = -250 a) ?l? level output voltage (penirqn pin @ iout = 250 a) vol - - 0.3 v (sda pin @ iout = 3ma) tri-state leakage current ( note 6 ) iolk all pins expect for xp, yp, xn, yn pins -10 10 a xp, yp, xn, yn pins -10 10 a note 6. expect for test pin. test pin has internal pull-down device, nominally 100k ? . ms1068-e-04 2011/03 - 5 - [AK4186] switching characteristics (ta=-40 c to 85 c, vdd=1.6v to 3.6v) parameter symbol min typ max units internal oscilator clock frequency f 2.5 3.6 5.1 mhz osc touch panel (a/d converter) scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 7 ) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s pulse width of spike noise suppressed by input filter tsp 0 - 50 ns capacitive load on bus cb - - 400 pf note 7: data must be held for sufficient time to bridge the 300ns transition time of scl. thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 2. timing diagram ms1068-e-04 2011/03 - 6 - [AK4186] operation overview function overview the AK4186 consists of the following blocks: 1.6v successive approximation resister (sar) a/d converter 4-wire or 5-wire resistive touch screen controller interface single or continuous a/d conversion internal clock for sar a/d converter 2 i c tm i/f a/d converter for touch screen the AK4186 integrates a 12bit successive approximation re sistor (sar) a/d converter for position measurement, temperature, and auxiliary input. the architecture is base d on capacitive redistribution algorithm, and an internal capacitor array functions as the sample/hold (s/h) circuit. the sar a/d converter output is a straight binary format as shown below: input voltage output code fffh ( & vref-1.5lsb)~ & vref ffeh ( & vref-2.5lsb) ~ ( & vref-1.5lsb) --------- --------- 0.5lsb ~ 1.5lsb 001h 0 ~ 0.5lsb 000h & vref: (vref+) ? (vref-) table 1. output code the f osc clock of an internal oscillator is used for a/d conversion. the full scale ( & vref) of the a/d converter depends on the input mode. position and pen pressure are measured in differential mode, and then in is measured in single-ended mode. the AK4186 is controlled by 8bit serial command. a/d conversion result is 12bit data output on the sda pin. analog inputs the analog input channel is automatically selected in sequential measurement mode. when position detection (x-axis and y-axis) and pen pressure are selected as anal og inputs in differential mode, the full scale ( & vref) is the voltage difference between the non-inverting terminal and the in verting terminal of the measured axis (e.g. x-axis measurement: (xp) ? (xn)). analog input to a/d converters ( & ain) is the voltage difference between the non- inverting terminal of the non-measured axis and the inverting terminal of the measured axis. at single-ended mode, the full scale of a/d converter ( & vref) is the voltage difference between the vdd and the vss. the analog input of a/d converter ( & ain) is the voltage difference between th e selected channel (in) and the vss. if the source of analog input is high impedance, longer tracking time is required. then a/d conversion should be started. status of driver switch adc input ( & ain) reference voltage ( & vref) channel selection ref. mode x-driver y-driver ain+ ain- vref+ vref- ain measure off off in gnd vref gnd ser x-axis measure on off yp xn xp xn dfr y-axis measure off on xp yn yp yn dfr z1 measure (pressure) xn-on yp-on xp xn yp xn dfr z2 measure (pressure) xn-on yp-on yn xn yp xn dfr table 2. measurement mode (4-wire) ms1068-e-04 2011/03 - 7 - [AK4186] status of driver switch adc input ( ain) reference voltage ( vref) channel selection ref. mode tl-driver br-driver ain+ ain- vref+ vref- x-axis measure on off wiper tl br tl dfr y-axis measure off on wiper br tl br dfr table 3. measurement mode (5-wire) position detection of touch screen 1. the position detection for 4-wire touch screen the position on the touch screen is detected by taking the voltage of one axis when the voltage is supplied between the two terminals of another axis. at least two a/d conversions ar e needed to get the two-dimensions (x/y-axis) position. the x-plate and y-plate are connected on the dotted line when the panel is touched. x+ x- x-plate (top side) y-plate (bottom side) c) 4-wire touch screen construction x-plate y-plate x-plate y+ y- yn xn yp xn-driver sw on vref+ vref adc ain+ ain- xp xp-driver sw on a) x-position measurement differential mode b) y-position measurement differenti al mode yn xn yp yn-driver sw on vr ef+ vr ef- adc ain+ ain- xp yp-driver sw on vdd vdd tou ch scre en y- p l a t e figure 3. axis measurements for 4-wire touch screen ms1068-e-04 2011/03 - 8 - [AK4186] 2. the position detection for 5-wire touch screen a 5-wire touch panel consists of one transparent resistiv e layer and a top metal contact area separated by insulating spacers. the top layer acts only as a voltage measuring probe, the position detection uses th e bottom resistive layer that had metal contacts at the 4 corners. when the top layer is pr essed by a pen or stylus, the top layer contacts with the bottom layer. then the x and y coordinates is detected. the 5-wire touch screen works properly even with damages or scratches on the top layer, therefore the 5-wire touch pane l has higher durability than the 4-wire touch panel. connect the metal contact of the top layer to the wiper pin to measur e the y-axis of current position at ain+. the top right and top left contacts at the 4 corners are connected to vdd and the bottom right and bottom left contacts connected to vss. then the AK4186 initiates a/d conversion of ain+ input voltage, and y-axis position is determined. terminal tl tr bl br x-axis vss vdd vss vdd y-axis vdd vdd vss vss switch vdd vss switch sw vdd/vss on/off on/off vdd/vss table 4. driver sw configuration tl sw on bl sw on bl adc vdd bl tr wiper vref+ vref adc ain+ ain- tr a) x-position measurement differential mode tl bl sw on br sw on br tr sw on vdd br sw on br tr sw on b) y-position measurement differential mode vr ef+ vr ef- ain+ ain- vdd tl vdd wiper tl sw on the top layer and bottom layer are connected on the dotted line when the panel is touched. tl bl detection side (top layer) drive side (bottom layer) 5-wire touch screen construction tr br adc wiper figure 4. axis measurements for 5-wire touch screen ms1068-e-04 2011/03 - 9 - [AK4186] pen pressure measurement (only 4-wire touch screen) the touch screen pen pressure can be derived from the m easurement of the contact resi stor between two plates. the contact resistance depends on the size of the depressed area an d the pressure. the area of the spot is proportional to the contact resistance. this resistance (rtouch) can be calculated using two different methods. the first method is that when the total resistance of the x-plate sheet is alr eady known. the resistance, rtouch, is calculated from the results of three conversions, x-position, z1-position, and z2-p osition, and then using following formula: ? ? ? ? ? ? ? ? ? ?= 1 z z 4096 x rr 1 2 position plate-x touch the second method is that when both the resistances of th e x-plate and y-plate are known. the resistance, rtouch, is calculated from the results of three conversions, x-position, y-position, and z1-position, and then using the following formula: ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? = 4096 y -1r1 z 4096 4096 xr r position plate-y 1 position plate-x touch on yn vref+ vref- adc ain+ ain- xp yp xn on a) z1-position measurement differential mode touch on yn vref+ vref- adc ain+ ain- xp yp xn on b) z2-position measurement differential mode touch vdd vdd figure 5. pen pressure measurements ms1068-e-04 2011/03 - 10 - [AK4186] digital i/f the AK4186 is controlled by a microprocessor via i 2 c bus and supports standard mode (100khz) and fast mode (400khz). note that the AK4186 operates in those two modes and does not support a high speed mode i 2 c-bus system (3.4mhz). the AK4186 can operate as a slave device on the i 2 c bus network. the AK4186 operates off of supply voltage down to 1.6v in order to connect a low voltage microprocessor. micro- processor i 2 c bus controller AK4186 scl sda 4/5-wire touch panel penirqn rp rp vdd=1.6v ~ 3.6v cad0 ?l? or ?h? figure 6. digital i/f 1. write operations figure 7 shows the data transfer sequence for the i 2 c-bus mode. all commands are preceded by start condition. a high to low transition on the sda line while scl is high indicates start condition ( figure 11 ). after the start condition, a slave address is sent. this address is 6 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant five bits of the slave ad dress are fixed as ?100100?. the next bit is cad0 (device address bit). this bit identify the speci fic device on the bus. the hard-wired input pin (cad0 pin) set this device address bit ( figure 8 ). if the slave address matches that of the ak41 86, the AK4186 generates an acknowledge and the operation is executed. the master must generate the ack nowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 12 ). r/w bit value of ?1? indicates that the read operation is to be executed. ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the AK4186. the format is msb first, and those most significant two bits are fixed to zeros ( figure 9 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 10 ). the AK4186 generates an acknowledge after each byte is received. a data transfer is always terminated by stop condition generated by the master. a low to high transition on the sda line while scl is high defines stop condition ( figure 11 ). the AK4186 can perform more than one by te write operation per sequence. after receipt of the thir d byte the AK4186 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. if th e address exceeds 1fh prior to generating stop condition, the address counter will ?roll ove r? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. high or low state of the data line can only change when the clock signal on the scl line is low ( figure 13 ) except for the start and stop conditions. ms1068-e-04 2011/03 - 11 - [AK4186] sda s t a r t ak 41 86 ack s sla ve a ddress data (n) p s t o p r/w = ?0? su b a ddress(n) AK4186 ack AK4186 ack AK4186 ack data (n+1) data (n+x) AK4186 ac k AK4186 ack figure 7. data transfer sequence at the i 2 c-bus mode 1 0 0 1 0 0 cad0 r/w (this cad0 should match with cad0 pin.) figure 8. the first byte 0 0 a5 a4 a3 a2 a1 a0 figure 9. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 10. byte structure after the second byte scl sda stop condition start condition s p figure 11. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 12. acknowledge on the i 2 c-bus ms1068-e-04 2011/03 - 12 - [AK4186] scl sda data line stable; data valid change of data allowed 2 figure 13. bit transfer on the i c-bus 2. read operations set the r/w bit = ?1? for the re ad operation of the AK4186. (1) register read operation after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cycle after the recei pt of the first data word. after receiv ing each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 1fh prior to generating stop cond ition, the address counter w ill ?roll over? to 00h and the data of 00h will be read out. the register read operation a llows the master to access any memory location at random. prior to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy? write operation. the master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. af ter the register address is acknowledged, the master immediately reissues the start request and th e slave address with the r/w bit ?1?. the AK4186 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledge but generates stop condition instead , the AK4186 ceases transmission. a/d conversion data in sequence mode can be read wh en the data is available. sda s t a r t ak418 6 ac k s slave a dd ress data (n) p s t o p r/w= ?1? data (n+1) data (n+x) mast r ac k mast r ac k mast r ack mast r nack ak418 6 ac k s slave a ddress r/w = ?0? ak41 8 6 ack sub a ddr ess(n ) s t a r t figure 14. register address read (2) a/d measurement operation when the master send a read command after sending a c ontrol register address for a measurement channel by a write operation, the AK4186 starts a/d conversion in singl e mode. the master issues the slave address with the r/w bit ?1?. the AK4186 then generates an acknowledge, and outputs adc data. the adc data is 2 bytes format (msb first), and upper 12-bit are valid and lower 4-bit are filled with ?0?. ( figure 17 , figure 18 ) the master receives the first byte, and generates an acknowledge. then the master receives the second byte a nd does not generate an acknowledge, the AK4186 ceases transmission. ( figure 15 ) if the master generates an acknowl edge, the AK4186 newly repeats a/d conversion to set the channel every read cycle, and the master can receive update adc data on each read operation. the AK4186 repeats a/d conversion and continuously outputs adc data until the master does not generate an acknowledge but generates a stop condition instead. ( figure 16 ) this continuous read mode enables the higher sampling rate and lower processor load than a single adc data read. ms1068-e-04 2011/03 - 13 - [AK4186] sda s t a r t ak418 6 ac k s slave a dd ress a dcdata (high byte) p s t o p r/w = ?1? a dc data (lo w b yte ) maste r ac k maste r nac k ak418 6 ac k s slave a ddress r/w = ?0? ak 41 86 ack sub a ddr ess(n ) s t a r t figure 15. single adc data read sda s t a r t s sl ave a ddress a dc data (high byte) s t o p r/w= ?1? a dc data (low byte) a dc data (high byte) a dc data (low byte) a dc data (h igh byte) p a dc data (low byte) ak 41 8 6 ack maste r ac k maste r ac k master ack maste r ac k maste r ac k maste r nack maste r ack ak 41 8 6 ac k s sl ave a ddress r/w= ?0? ak418 6 ac k su b a ddress(n) s t a r t figure 16. continuous adc data read d11 d10 d9 d8 d7 d6 d5 d4 figure 17. adc data (high byte) d3 d2 d1 d0 0 0 0 0 figure 18. adc data (low byte) ms1068-e-04 2011/03 - 14 - [AK4186] register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h system reset 0 0 0 0 0 0 0 srst 01h setup command panel 0 sleep1 sleep0 0 0 0 pd0 02h sequence command 0 se qm2 seqm1 seqm0 count interval2 interval1 interval0 03h reserved 0 0 0 0 0 0 0 0 -0fh 10h status chst3 chst2 chst1 chst 0 seqst3 seqst2 seqst1 seqst0 11h sequence data 1h d1t11 d1t10 d1 t9 d1t8 d1t7 d1t6 d1t5 d1t4 12h sequence data 1l d1t3 d1t2 d1t1 d1t0 0 0 0 0 13h sequence data 2h d2t11 d2t10 d2 t9 d2t8 d2t7 d2t6 d2t5 d2t4 14h sequence data 2l d2t3 d2t2 d2t1 d2t0 0 0 0 0 15h sequence data 3h d3t11 d3t10 d3 t9 d3t8 d3t7 d3t6 d3t5 d3t4 16h sequence data 3l d3t3 d3t2 d3t1 d3t0 0 0 0 0 17h sequence data 4h d4t11 d4t10 d4 t9 d4t8 d4t7 d4t6 d4t5 d4t4 18h sequence data 4l d4t3 d4t2 d4t1 d4t0 0 0 0 0 19h reserved 0 0 0 0 0 0 0 0 -1fh 20h single xh xs11 xs10 xs9 xs8 xs7 xs6 xs5 xs4 21h single xl xs3 xs2 xs1 xs0 0 0 0 0 22h single yh ys11 ys10 ys9 ys8 ys7 ys6 ys5 ys4 23h single yl ys3 ys2 ys1 ys0 0 0 0 0 24h single z1h z1s11 z1s10 z1s9 z1s8 z1s7 z1s6 z1s5 z1s4 25h single z1l z1s3 z1s2 z1s1 z1s0 0 0 0 0 26h single z2h z2s11 z2s10 z2s9 z2s8 z2s7 z2s6 z2s5 z2s4 27h single z2l z2s3 z2s2 z2s1 z2s0 0 0 0 0 28h single inh ins11 ins10 ins9 ins8 ins7 ins6 ins5 ins4 29h single inl ins3 ins2 ins1 ins0 0 0 0 0 table 5. AK4186 register map ms1068-e-04 2011/03 - 15 - [AK4186] system reset upon power-up, the AK4186 must be reset by writing the reset command. (refer to the ? ? for details) this ensures that all internal register reset to thei r initial values (00h) and set the channel to x-axis (auto drive r = off). the system reset can also stop a sequential measurement forcibly, but all data will be cleared. sda s t a r t ak41 8 6 ac k s sla ve a ddress rese t command p s t o p r/w= ?0? su b a ddress ak418 6 ac k ak 41 86 ac k figure 19. data transfer sequence at the system reset 1 0 0 1 0 0 cad0 r/w (those cad1/0 should match with cad1/0 pins.) figure 20. the first byte 0 0 0 0 0 0 0 0 figure 21. the second byte 0 0 0 0 0 0 0 1 figure 22. byte structure at reset command setup function of touch panel 1. setup command configuration addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h setup command panel 0 sleep1 sleep0 0 0 0 pd0 table 6. setup command register format ms1068-e-04 2011/03 - 16 - [AK4186] bits name description d7 panel panel type selection 0: 4-wire (default) 1: 5-wire d6 reserved must write ?0? d5-d4 sleep1-0 sleep command bits (refer to ? sleep mode ?) 00: normal mode (default) 01: sleep mode 1 (penirqn disabled and output ?h?. touch panel is open.) 10: sleep mode 2 (penirqn disabled and open. touch panel is open.) 11: reserved d3 reserved must write ?0? d2 reserved must write ?0? d1 reserved must write ?0? d0 pd0 power-down mode (refer to ? power-down control ?) 0: auto power-down mode (default) 1: driver on mode table 7. setup command description sleep1-0, pd0 bits can be written du ring a sequential measurement but panel bit will not be changed. 2. sequence command configuration addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h sequence command 0 seqm2 seqm1 seqm0 count interval2 interaval1 interval0 table 8. sequence command register format the AK4186 starts a/d conversion in sequence mode by setting the count, seqm2-0, interval2-0 bits of the register address to 02h. the AK4186 makes six or ten measurements by setting the count bit. the results are used to calculate the average value, discarding the minimum and maximum values, and the result sets the data register of sequence mode. if the address 02h is set again during a se quential measurement, this setting is ignored and the AK4186 continues the measurement. the master ex ecutes the register read operation to read the measurement data of sequence mode after confirming the penirqn pi n turns to ?h? (data available). bits name description d7 reserved must write ?0? d6-d4 seqm2-0 sequence mode 000: x y z1 z2 scan (only 4-wire touch screen) (default) 001: x y scan 010: x scan 011: y scan 100: z1 z2 scan (only 4-wire touch screen) 101: reserved 110: a-in (only 4-wire touch screen) 111: reserved d3 count a/d conversion count 0: 6 times a/d conversion (default) 1: 10 times a/d conversion d2-d0 interval2-0 sampling interval times. 000: 0 s (default) 001: 5 s 010: 10 s 011: 20 s 100: 50 s 101: 100 s 110: 200 s 111: 500 s table 9. sequence command description ms1068-e-04 2011/03 - 17 - [AK4186] data register 1. sequence mode data register the AK4186 starts a/d conversion in sequence mode by setting the count, seqm2-0, interval2-0 bits of the register address 02h. the AK4186 makes six or ten measurements by se tting the count bit. the results are used to calculate the average value, discarding the minimum and maximum values, and the result sets the data register of sequence mode. the AK4186 registers data from address 11h in order of setting the seqm2-0 bits. the master can read the adc data by the register read operation after confirming the penirqn pin turns to ?h? or a register status seqst3-0 = 02h (data available). the data register is read clear so that data will be deleted once it is read. do not read data during a se quential measurement. addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h status chst3 chst2 chst1 chst 0 seqst3 seqst2 seqst1 seqst0 11h sequence data 1h d1t11 d1t10 d1 t9 d1t8 d1t7 d1t6 d1t5 d1t4 12h sequence data 1l d1t3 d1t2 d1t1 d1t0 0 0 0 0 13h sequence data 2h d2t11 d2t10 d2 t9 d2t8 d2t7 d2t6 d2t5 d2t4 14h sequence data 2l d2t3 d2t2 d2t1 d2t0 0 0 0 0 15h sequence data 3h d3t11 d3t10 d3 t9 d3t8 d3t7 d3t6 d3t5 d3t4 16h sequence data 3l d3t3 d3t2 d3t1 d3t0 0 0 0 0 17h sequence data 4h d4t11 d4t10 d4 t9 d4t8 d4t7 d4t6 d4t5 d4t4 18h sequence data 4l d4t3 d4t2 d4t1 d4t0 0 0 0 0 table 10. data register for sequence mode (read only) bit name description d7-d4 chst3-0 last measurement channel for single mode 0011: ain 0100: x-axis 0101: y-axis 0110: z1 0111: z2 others: reserved d3-d0 seqst3-0 status bits for sequence mode 0000: not busy 0001: sequence busy 0010: data available others: reserved table 11. status register description (read only) ms1068-e-04 2011/03 - 18 - [AK4186] 2. single mode data register the AK4186 starts a/d conversion in si ngle mode by receiving a single measurement command, and then outputs msb first 12bit a/d data. addr register name d7 d6 d5 d4 d3 d2 d1 d0 20h single xh xs11 xs10 xs9 xs8 xs7 xs6 xs5 xs4 21h single xl xs3 xs2 xs1 xs0 0 0 0 0 22h single yh ys11 ys10 ys9 ys8 ys7 ys6 ys5 ys4 23h single yl ys3 ys2 ys1 ys0 0 0 0 0 24h single z1h z1s11 z1s10 z1s9 z1s8 z1s7 z1s6 z1s5 z1s4 25h single z1l z1s3 z1s2 z1s1 z1s0 0 0 0 0 26h single z2h z2s11 z2s10 z2s9 z2s8 z2s7 z2s6 z2s5 z2s4 27h single z2l z2s3 z2s2 z2s1 z2s0 0 0 0 0 28h single inh ins11 ins10 ins9 ins8 ins7 ins6 ins5 ins4 29h single inl ins3 ins2 ins1 ins0 0 0 0 0 table 12. data register for single mode (read only) power-down control power-down and pen interrupt function are controlled by pd0 bit. in order to achieve minimum current, it is recommended to set pd0 bit = ?0? for automatic power down of the touch screen driver after a/d conversion. it is possible to reduce the variation in data by setting pd0 bit = ?1? during measurements. a/d converter keeps power up state after every measurement completed. when the register data of address 01h is written, pd0 bit is updated at the rising edge of the 27th scl. the last pd0 bit is valid until this timing. the a/d converter and internal oscillator are automatically powered up at the start of the conversion, and automatically powered down at the end of the conversion, regardless of the pd0 bit setting. pd0 penirqn function 0 enable auto power-down mode in power-down state, the touch screen driver switches are powered down. (only yn or bl driver switch is turned on and fo rced to vss.) pen interrupt function is enabled except when in the sa mpling time and converting time. 1 disable driver on mode if x-axis or y-axis is selected as analog input, touch screen driver switches are always powered up. this is effective when more settling time is required to suppress the electrical bouncing of touch plate. pen interrupt function is disabled and penirqn is forced to ?l? state. table 13. power-down control ms1068-e-04 2011/03 - 19 - [AK4186] sleep mode the AK4186 supports sleep mode that puts touch panel to open state and disables pen interrupt function, effective for reducing power consumption caused by unnecessary pen touch. sleep mode is controlled by sleep1-0 bits. the AK4186 change s to sleep mode on the risi ng edge of 27th scl after the micro-controller writes ?01? or ?10? to sleep1-0 bits of AK4186?s register. all touc h screen driver switches and a/d converter are powered down in this sleep mode, and it reduces power consumption to the minimum value. the penirqn output is shown below. ( table 14 ) the AK4186 returns to normal operation out of sleep mode when the micro-controller writes ?00? to sleep1-0 bits. the timing of going back to normal operation mode is the rising edge of the 27th scl. the initial state after system reset is in normal operation mode. sleep1-0 penirqn touch panel 00 normal operation normal operation 01 disable (penirqn=h) open 10 disable (penirqn=hi-z) open 11 n/a n/a table 14. sleep mode a/d conversion is available during sleep mode by issuing an adc executing command (sequential). the AK4186 returns to sleep mode after completing an a/d conversion. ms1068-e-04 2011/03 - 20 - [AK4186] control sequence power-up sequence to fix the i 2 c interface statement, send a dummy command when first power up. after the dummy command, send a reset command to initialize internal registers. 1 0 0 1 0 0 cad0 r/w figure 23. slave address construction (cad0 is set by a pin) 1 1 1 1 1 1 1 1 figure 24. dummy address construction 1 1 1 1 1 1 1 1 figure 25. dummy command construction sda s t a r t AK4186 ack or nac k s slave a ddress dumm y command p s t o p r/w= ?0? dumm y a ddress s t a r t AK4186 ac k s slave a ddress reset command p s t o p r/w= ?0? sub a ddress AK4186 ac k AK4186 ac k AK4186 ack or nac k AK4186 ack or nac k dummy command reset command figure 26. power-up sequence ms1068-e-04 2011/03 - 21 - [AK4186] touch screen controller control sequence (single mode) (1) setup sequence in case of the single measurement mode, this touch panel configuration register sets the measurement mode of the AK4186. touch screen driver switches are turned on at driver on mode (pd0 bit = ?1?) on the rising edge of the 27th scl. it is possible to have longer tracking time even if the source of analog input impeda nce is high, because the actual sampling is executed at the read operation. if a current measurement is made by the same setting of pd0 bit as the last time, the setup sequence is unnecessary. AK4186 ack 0 AK4186 ack pa nel 0 pd 0 = 0 ? o ff? 0 0 stop pd0 =1 0 sleep 1 pd0 cad0 19 data byte 21 22 23 24 25 26 27 20 0 sub address byte AK4186 ack slave address byte r egist er addr = 01h start 1 0 0 18 0 touch screen driver sw sleep 0 16 scl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 sda 1 0 0 0 0 r/ w figure 27. setup operation and driver sw timing (2) single measurement sequence when the master send a read command after sending a c ontrol register address for a measurement channel by a write operation, the AK4186 starts a/d conversion in single mode. this a/d conversion is synchronized with the internal clock. the internal oscillator of the AK4186 is automatically powered up on the falling edge of 25th scl after writing the register address, and the AK4186 samples the an alog input and completes a/d conversion after the rising edge of 26th scl. the master receives the first byte of se rial data (d11-d4, msb first) , and generates an acknowledge. then the master receives the second byte of serial data (d 3-d0, followed by four 0 bits). when the master continuously reads adc data, the master repeats read operation after ge nerating an acknowledge. if the master does not generate an acknowledge but generates stop condition instead, the AK4186 ceases continuous operation. touch screen driver sw scl sda start 1 0 0 0 0 1 0 0 AK4186 ack r/ w slave address byte data byte (msb) data byte (lsb) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ?h? pd0=?1? pd0=?0? sampling ad conv. 0 register addr = 20h~28h sub address byte stop osclk cad 0 penirqn pd0=?0? enable enable ?l? r/ w start 1 0 0 1 0 1 0 0 cad 0 AK4186 ack slave address byte 33 34 35 36 37 38 39 40 41 42 43 44 45 46 AK4186 ack d10 d9 d8 d7 d6 d4 d5 d11 master ack 1 d2 d1 d0 0 0 0 0 d3 master ack ad conv. sampling figure 28. single measurement operation and driver sw timing ms1068-e-04 2011/03 - 22 - [AK4186] touch screen controller control sequence (sequence mode) the AK4186 starts a/d conversion in sequence mode by setting the count, seqm2-0, interval2-0 bits of the register address 02h. penirqn is forced to ?l? state, and internal oscillator is automatically powered up. the AK4186 makes six or ten measurements by setting the count bit. the results are used to calculate the average value, discarding the minimum and maximum values, and the result sets the data register of sequence mode. when the sequence is finished, the AK4186 sets the penirqn pin to ?h? and notifies that sequence is ended. after 20 s (typ.) is passed from the rising edge of the penirqn pin, the intern al oscillator is powered down and pen interrupt function is enabled. the master executes the register read operation to read the meas urement data of sequence mode after confirming data availability. the master can confirm data availability by penirqn or seqst3-0 = 03h. this sequence data can be read in register read operation one by one (address 11h). prio r to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy ? write operation. the master issues start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register addres s is acknowledged , the master immediately reissues the start request and the slave address with the r/w bit ?1?. the AK4186 then generates an acknowledge, 1 byte of adc data, and increments the internal address counter by 1. if the master does not generate an acknowledge but generates stop condition instead, the AK4186 ceases transmission. the a/d data is cleared after reading all the a/d data. pen touch count end? sequence start start clock set penirqn low driver set wait time r stop clock & pentouch enable done no yes adc sequence end? no yes set penirqn high figure 29. internal clock mode control flowchart ms1068-e-04 2011/03 - 23 - [AK4186] internal sequ ence (seqm2-0 b its=?0 01?, x-y scan) slave address penirqn s w scl sda osclk 20 / fosc tracking, conversion (x-axis 1st) pen touch wait 20 / fosc tracking, conversion (x-axis nth) 20 / fosc tracking, co nversion (y-axis 1st) 20 / fosc tracking, conversion (y-axis nth) wait w=0 dav penirqn ena ble sub address (02h) data (10h) p figure 30. sequence mode control sequence (x-y scan: seqm bits = ?001?) (sequence mode start internal sequence processing data available) slave address penirqn s w scl sda w=0 sub address (11h) p adc data (1 2h) adc data (13h ) adc data (14h) dav AK4186 ack AK4186 ack ack ack ack master nack master master master r r=1 AK4186 ack adc data (11h) slave ad dress s figure 31. sequence mode control sequence (x-y scan: seqm bits = ?001?) (data available a/d data read) d11 d10 d9 d8 d7 d6 d5 d4 (msb) figure 32. adc data (high byte) d0 d3 d2 d1 0 0 0 0 (lsb) figure 33. adc data (low byte) ms1068-e-04 2011/03 - 24 - [AK4186] pen interrupt the AK4186 has pen interrupt function to detect pen touches. pen interrupt function is enabled at power-down state and pd0 bit = ?0? ( figure 34 ). the yn pin (4-wire) or bl pin (5-wire) is connected to vss at the pen interrupt enabled state. the xp pin (4-wire) or wiper pin (5-wire) is pulled up via an internal resistor (r irq : typ.50k ? ). penirqn is connected to the xp pin (4-wire) or wiper pin (5-wire) inside. if touch plate is pressed by a pen, the current flows via [AK4186] system design figure 35 , figure 36 , figure 37 , figure 38 shows the system connection diagram for the AK4186. the evaluation board [akd4186] demonstrates the optimum layout, power supply arrangements and measurement results. AK4186ecb <4-wire touch screen input> top vie w cad 0 analog suppl y 1.6 3.6v 0.001 * p scl sda penirqn in yn xn yp xp vss tes t vdd + 10 0.1 4-wire touch screen auxiliary analog input 0.001 * 0.001 * 0.001 * a nalog ground digital ground rp rp ?l? or ?h? figure 35. typical connection diagram (4-wire, AK4186ecb) notes: - vss of the AK4186 should be distributed separately from the ground of external controllers. - all digital input pins (scl, sda, cad0 pins) must not be left floating. ms1068-e-04 2011/03 - 26 - [AK4186] AK4186en <4-wire touch screen input> auxiliary analog input 0.001 * analog suppl y 1.6 3.6v 0.001 * p 10 0.1 4-wire touch screen 0.001 * 0.001 * a nalog ground digital ground rp rp ?l? or ?h? + nc vss test nc y n x n yp xp sc l sda penirqn cad0 nc vdd in nc AK4186en top view 1 3 14 15 16 12 11 10 1 8 7 6 5 9 2 3 4 figure 36. typical connection diagram (4-wire, AK4186en) notes: - vss of the AK4186 should be distributed separately from the ground of external controllers. - all digital input pins (scl, sda, cad0 pins) must not be left floating. ms1068-e-04 2011/03 - 27 - [AK4186] AK4186ecb <5-wire touch screen input> 0.001 * 5-wire touch screen 0.001 * 0.001 * 0.001* a nalog ground digital ground 0.001 * to p vie w cad 0 analog suppl y 1.6 3.6v p scl sda penirqn wipe r bl tl t r b r vss tes t vdd + 10 0.1 rp rp ?l ? or ?h ? figure 37. typical connection diagram (5-wire, AK4186ecb) notes: - vss of the AK4186 should be distributed separately from the ground of external controllers. - all digital input pins (scl, sda, cad0 pins) must not be left floating. ms1068-e-04 2011/03 - 28 - [AK4186] ms1068-e-04 2011/03 - 29 - AK4186en <5-wire touch screen input> 0.001 * analog suppl y 1.6 3.6v 0.001 * p 10 0.1 5-wire touch screen 0.001 * 0.001 * a nalog ground digital ground rp rp ?l? or ?h? + nc vss test nc b l tl tr bp sc l sda penirqn cad0 nc vdd wiper nc AK4186en top view 1 3 14 15 16 12 11 10 1 8 7 6 5 9 2 3 4 0.001 * figure 38. typical connection diagram (5-wire, AK4186en) notes: - vss of the AK4186 should be distributed separately from the ground of external controllers. - all digital input pins (scl, sda, cad0 pins) must not be left floating. 1. grounding and power supply decoupling the AK4186 requires careful attention to power supply and grounding arrangements. vdd is usually supplied from the system?s analog supply. vss of the AK4186 must be connected to the analog ground plane. system analog ground and digital ground should be connected together near to wher e the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK4186 as possible, with the small value ceramic capacitor being the nearest. 2. analog inputs when an emi source is close to the touch panel analog signal line, emi noise affects analog characteristics performance. connect noise canceling capa citors (*) as close as possible to each pin (xp, xn, yp, yn pins) of the AK4186 to avoid this noise. ( figure 35 , figure 36 , figure 37 , figure 38 ) [AK4186] ms1068-e-04 2011/03 - 30 - package (AK4186ecb) 12pin csp (unit: mm) 0.40 0.27 0.05 0.08 s s 0.05 ab s b m a 0.19 0.05 d cb a 1.26 0.05 top view bottom view 1.66 0.05 1 2 3 0.65 0.05 (0.23) (0.23) 0.40 xxxx material & lead finish package molding compound: epoxy resin, halogen (bromine and chlorine) free solder ball material: snagcu [AK4186] ms1068-e-04 2011/03 - 31 - package (AK4186en) 16pin qfn (unit: mm) 3.000.07 1.50 1 16 exposed pad 1.80 0.70 s a 1.80 0.05max 0.50 0.220.05 0.300.07 0.05 s m 0.05 s a b 3.000.07 1.50 0.75 max c0.30 top view bottom view b 13 12 9 8 4 part a 0.17~0.27 0.00~0.05 0.12~0.18 [part a detail] note: the thermal die pad must be open or connected to the ground. package & lead frame material package molding compound: epoxy resin, halogen (bromine and chlorine) free lead frame material: cu alloy lead frame surface treatment: palladium plate [AK4186] marking (AK4186ecb) a1 x xxx date code: xxxx(4 digits) pin #a1 indication marking (AK4186en) 4186 x xx x x date code: xxxxx (5 digits) pin #1 indication ms1068-e-04 2011/03 - 32 - [AK4186] revision history date (yy/mm/dd) revision reason page/line contents 09/03/30 00 first edition 09/10/22 01 error correction 18 sequence mode data register /2 ?register address 03h? ?register address 02h? /6 seqst7-0 = 03h seqst3-0 = 02h 22 setup sequence figure 27 was changed. 10/07/02 02 product AK4186en was added. addition 10/12/15 03 spec change 5 analog characteristics gain error (AK4186en): -6 -4.5 (min) +2 +3.5 (max) 11/03/30 04 error correction 3 pin/function pin no. d3, 12: bl ?touch panel bottom right input? ?touch panel bottom left input? important notice " these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. " descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporatio n of these external circuits, applicati on circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. " any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to cu stoms and tariffs, currency exchange, or strategic materials. " akm products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medi cine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. " it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all resp onsibility and liability for and hold akm harmless from any and all claims arising from th e use of said product in the absence of such notification. ms1068-e-04 2011/03 - 33 - |
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